// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/05/CPU.hdl

/**
 * The Hack CPU (Central Processing unit), consisting of an ALU,
 * two registers named A and D, and a program counter named PC.
 * The CPU is designed to fetch and execute instructions written in 
 * the Hack machine language. In particular, functions as follows:
 * Executes the inputted instruction according to the Hack machine 
 * language specification. The D and A in the language specification
 * refer to CPU-resident registers, while M refers to the external
 * memory location addressed by A, i.e. to Memory[A]. The inM input 
 * holds the value of this location. If the current instruction needs 
 * to write a value to M, the value is placed in outM, the address 
 * of the target location is placed in the addressM output, and the 
 * writeM control bit is asserted. (When writeM==0, any value may 
 * appear in outM). The outM and writeM outputs are combinational: 
 * they are affected instantaneously by the execution of the current 
 * instruction. The addressM and pc outputs are clocked: although they 
 * are affected by the execution of the current instruction, they commit 
 * to their new values only in the next time step. If reset==1 then the 
 * CPU jumps to address 0 (i.e. pc is set to 0 in next time step) rather 
 * than to the address resulting from executing the current instruction. 
 */

CHIP CPU {

    IN  inM[16],         // M value input  (M = contents of RAM[A])
        instruction[16], // Instruction for execution
        reset;           // Signals whether to re-start the current
                         // program (reset==1) or continue executing
                         // the current program (reset==0).

    OUT outM[16],        // M value output
        writeM,          // Write to M? 
        addressM[15],    // Address in data memory (of M)
        pc[15];          // address of next instruction

    PARTS:
    ALU(x=dreg, y=aluy, zx=instruction[11], nx=instruction[10], zy=instruction[9], ny=instruction[8], f=instruction[7], no=instruction[6], out=aluout, out=outM, zr=aluzr, ng=alung);
    
    And(a=instruction[15], b=instruction[4], out=dload);
    DRegister(in=aluout, load=dload, out=dreg);

    Not(in=instruction[15], out=ainst);
    Or(a=instruction[5], b=ainst, out=aload);

    ARegister(in=aregin, load=aload, out=areg, out[0..14]=addressM);
    Mux16(a=instruction, b=aluout, sel=instruction[15], out=aregin);

    And(a=instruction[15], b=instruction[3], out=writeM);

    Mux16(a=areg, b=inM, sel=instruction[12], out=aluy);



    And(a=instruction[1], b=aluzr, out=jmpzr);
    And(a=instruction[2], b=alung, out=jmpng);

    Not(in=alung, out=alunng);
    Not(in=aluzr, out=alunzr);
    And(a=alunng, b=alunzr, out=alupz);
    And(a=instruction[0], b=alupz, out=jmppz);

    Or8Way(in[0]=jmpzr, in[1]=jmpng, in[2]=jmppz, out=jump);

    And(a=jump, b=instruction[15], out=sjump);

    PC(in=areg, load=sjump, inc=true, reset=reset, out[0..14]=pc);
}