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72 lines
3.0 KiB
Plaintext
72 lines
3.0 KiB
Plaintext
// This file is part of www.nand2tetris.org
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// and the book "The Elements of Computing Systems"
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// by Nisan and Schocken, MIT Press.
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// File name: projects/05/CPU.hdl
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/**
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* The Hack CPU (Central Processing unit), consisting of an ALU,
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* two registers named A and D, and a program counter named PC.
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* The CPU is designed to fetch and execute instructions written in
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* the Hack machine language. In particular, functions as follows:
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* Executes the inputted instruction according to the Hack machine
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* language specification. The D and A in the language specification
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* refer to CPU-resident registers, while M refers to the external
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* memory location addressed by A, i.e. to Memory[A]. The inM input
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* holds the value of this location. If the current instruction needs
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* to write a value to M, the value is placed in outM, the address
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* of the target location is placed in the addressM output, and the
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* writeM control bit is asserted. (When writeM==0, any value may
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* appear in outM). The outM and writeM outputs are combinational:
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* they are affected instantaneously by the execution of the current
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* instruction. The addressM and pc outputs are clocked: although they
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* are affected by the execution of the current instruction, they commit
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* to their new values only in the next time step. If reset==1 then the
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* CPU jumps to address 0 (i.e. pc is set to 0 in next time step) rather
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* than to the address resulting from executing the current instruction.
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*/
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CHIP CPU {
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IN inM[16], // M value input (M = contents of RAM[A])
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instruction[16], // Instruction for execution
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reset; // Signals whether to re-start the current
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// program (reset==1) or continue executing
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// the current program (reset==0).
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OUT outM[16], // M value output
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writeM, // Write to M?
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addressM[15], // Address in data memory (of M)
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pc[15]; // address of next instruction
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PARTS:
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ALU(x=dreg, y=aluy, zx=instruction[11], nx=instruction[10], zy=instruction[9], ny=instruction[8], f=instruction[7], no=instruction[6], out=aluout, out=outM, zr=aluzr, ng=alung);
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And(a=instruction[15], b=instruction[4], out=dload);
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DRegister(in=aluout, load=dload, out=dreg);
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Not(in=instruction[15], out=ainst);
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Or(a=instruction[5], b=ainst, out=aload);
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ARegister(in=aregin, load=aload, out=areg, out[0..14]=addressM);
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Mux16(a=instruction, b=aluout, sel=instruction[15], out=aregin);
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And(a=instruction[15], b=instruction[3], out=writeM);
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Mux16(a=areg, b=inM, sel=instruction[12], out=aluy);
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And(a=instruction[1], b=aluzr, out=jmpzr);
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And(a=instruction[2], b=alung, out=jmpng);
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Not(in=alung, out=alunng);
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Not(in=aluzr, out=alunzr);
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And(a=alunng, b=alunzr, out=alupz);
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And(a=instruction[0], b=alupz, out=jmppz);
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Or8Way(in[0]=jmpzr, in[1]=jmpng, in[2]=jmppz, out=jump);
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And(a=jump, b=instruction[15], out=sjump);
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PC(in=areg, load=sjump, inc=true, reset=reset, out[0..14]=pc);
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} |