mirror of
https://github.com/usatiuk/nand2tetris.git
synced 2025-10-29 00:27:49 +01:00
29 lines
1.3 KiB
Plaintext
29 lines
1.3 KiB
Plaintext
// This file is part of the materials accompanying the book
|
|
// "The Elements of Computing Systems" by Nisan and Schocken,
|
|
// MIT Press. Book site: www.idc.ac.il/tecs
|
|
// File name: projects/03/b/RAM512.hdl
|
|
|
|
/**
|
|
* Memory of 512 registers, each 16 bit-wide. Out holds the value
|
|
* stored at the memory location specified by address. If load==1, then
|
|
* the in value is loaded into the memory location specified by address
|
|
* (the loaded value will be emitted to out from the next time step onward).
|
|
*/
|
|
|
|
CHIP RAM512 {
|
|
IN in[16], load, address[9];
|
|
OUT out[16];
|
|
|
|
PARTS:
|
|
RAM64(in=in, load=load1, address=address[0..5], out=out1);
|
|
RAM64(in=in, load=load2, address=address[0..5], out=out2);
|
|
RAM64(in=in, load=load3, address=address[0..5], out=out3);
|
|
RAM64(in=in, load=load4, address=address[0..5], out=out4);
|
|
RAM64(in=in, load=load5, address=address[0..5], out=out5);
|
|
RAM64(in=in, load=load6, address=address[0..5], out=out6);
|
|
RAM64(in=in, load=load7, address=address[0..5], out=out7);
|
|
RAM64(in=in, load=load8, address=address[0..5], out=out8);
|
|
|
|
DMux8Way(in=load, sel=address[6..8], a=load1, b=load2, c=load3, d=load4, e=load5, f=load6, g=load7, h=load8);
|
|
Mux8Way16(a=out1, b=out2, c=out3, d=out4, e=out5, f=out6, g=out7, h=out8, sel=address[6..8], out=out);
|
|
} |