most pcb routed

This commit is contained in:
2025-02-09 12:50:55 +01:00
parent bebe4bcfef
commit 175959b29f
3 changed files with 4421 additions and 3296 deletions

File diff suppressed because it is too large Load Diff

View File

@@ -116,21 +116,21 @@
},
"rules": {
"max_error": 0.005,
"min_clearance": 0.0,
"min_connection": 0.0,
"min_clearance": 0.15,
"min_connection": 0.15,
"min_copper_edge_clearance": 0.5,
"min_hole_clearance": 0.25,
"min_hole_to_hole": 0.25,
"min_hole_to_hole": 0.5,
"min_microvia_diameter": 0.2,
"min_microvia_drill": 0.1,
"min_resolved_spokes": 2,
"min_resolved_spokes": 1,
"min_silk_clearance": 0.0,
"min_text_height": 0.8,
"min_text_thickness": 0.08,
"min_through_hole_diameter": 0.2,
"min_track_width": 0.0,
"min_via_annular_width": 0.1,
"min_via_diameter": 0.4,
"min_through_hole_diameter": 0.3,
"min_track_width": 0.15,
"min_via_annular_width": 0.15,
"min_via_diameter": 0.6,
"solder_mask_to_copper_clearance": 0.0,
"use_height_for_length_calcs": true
},
@@ -179,6 +179,7 @@
],
"track_widths": [
0.0,
0.15,
0.2,
0.25,
1.0
@@ -465,25 +466,8 @@
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.3,
"via_diameter": 0.4,
"via_drill": 0.2,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.15,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Thinner",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.25,
"via_diameter": 0.4,
"via_drill": 0.2,
"via_diameter": 0.6,
"via_drill": 0.3,
"wire_width": 6
}
],

View File

@@ -6903,6 +6903,15 @@
(hide yes)
)
)
(property "Pn" " EVQ-P7C01P"
(at 52.07 130.81 90)
(effects
(font
(size 1.27 1.27)
)
(hide yes)
)
)
(pin "2"
(uuid "f8ba8fe9-9af0-49b5-a117-ba64295c310b")
)