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Stepan Usatiuk
2021-04-21 17:01:42 +03:00
commit 281a96945a
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215
projects/03/a/Bit.cmp Normal file
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@@ -0,0 +1,215 @@
| time | in |load | out |
| 0+ | 0 | 0 | 0 |
| 1 | 0 | 0 | 0 |
| 1+ | 0 | 1 | 0 |
| 2 | 0 | 1 | 0 |
| 2+ | 1 | 0 | 0 |
| 3 | 1 | 0 | 0 |
| 3+ | 1 | 1 | 0 |
| 4 | 1 | 1 | 1 |
| 4+ | 0 | 0 | 1 |
| 5 | 0 | 0 | 1 |
| 5+ | 1 | 0 | 1 |
| 6 | 1 | 0 | 1 |
| 6+ | 0 | 1 | 1 |
| 7 | 0 | 1 | 0 |
| 7+ | 1 | 1 | 0 |
| 8 | 1 | 1 | 1 |
| 8+ | 0 | 0 | 1 |
| 9 | 0 | 0 | 1 |
| 9+ | 0 | 0 | 1 |
| 10 | 0 | 0 | 1 |
| 10+ | 0 | 0 | 1 |
| 11 | 0 | 0 | 1 |
| 11+ | 0 | 0 | 1 |
| 12 | 0 | 0 | 1 |
| 12+ | 0 | 0 | 1 |
| 13 | 0 | 0 | 1 |
| 13+ | 0 | 0 | 1 |
| 14 | 0 | 0 | 1 |
| 14+ | 0 | 0 | 1 |
| 15 | 0 | 0 | 1 |
| 15+ | 0 | 0 | 1 |
| 16 | 0 | 0 | 1 |
| 16+ | 0 | 0 | 1 |
| 17 | 0 | 0 | 1 |
| 17+ | 0 | 0 | 1 |
| 18 | 0 | 0 | 1 |
| 18+ | 0 | 0 | 1 |
| 19 | 0 | 0 | 1 |
| 19+ | 0 | 0 | 1 |
| 20 | 0 | 0 | 1 |
| 20+ | 0 | 0 | 1 |
| 21 | 0 | 0 | 1 |
| 21+ | 0 | 0 | 1 |
| 22 | 0 | 0 | 1 |
| 22+ | 0 | 0 | 1 |
| 23 | 0 | 0 | 1 |
| 23+ | 0 | 0 | 1 |
| 24 | 0 | 0 | 1 |
| 24+ | 0 | 0 | 1 |
| 25 | 0 | 0 | 1 |
| 25+ | 0 | 0 | 1 |
| 26 | 0 | 0 | 1 |
| 26+ | 0 | 0 | 1 |
| 27 | 0 | 0 | 1 |
| 27+ | 0 | 0 | 1 |
| 28 | 0 | 0 | 1 |
| 28+ | 0 | 0 | 1 |
| 29 | 0 | 0 | 1 |
| 29+ | 0 | 0 | 1 |
| 30 | 0 | 0 | 1 |
| 30+ | 0 | 0 | 1 |
| 31 | 0 | 0 | 1 |
| 31+ | 0 | 0 | 1 |
| 32 | 0 | 0 | 1 |
| 32+ | 0 | 0 | 1 |
| 33 | 0 | 0 | 1 |
| 33+ | 0 | 0 | 1 |
| 34 | 0 | 0 | 1 |
| 34+ | 0 | 0 | 1 |
| 35 | 0 | 0 | 1 |
| 35+ | 0 | 0 | 1 |
| 36 | 0 | 0 | 1 |
| 36+ | 0 | 0 | 1 |
| 37 | 0 | 0 | 1 |
| 37+ | 0 | 0 | 1 |
| 38 | 0 | 0 | 1 |
| 38+ | 0 | 0 | 1 |
| 39 | 0 | 0 | 1 |
| 39+ | 0 | 0 | 1 |
| 40 | 0 | 0 | 1 |
| 40+ | 0 | 0 | 1 |
| 41 | 0 | 0 | 1 |
| 41+ | 0 | 0 | 1 |
| 42 | 0 | 0 | 1 |
| 42+ | 0 | 0 | 1 |
| 43 | 0 | 0 | 1 |
| 43+ | 0 | 0 | 1 |
| 44 | 0 | 0 | 1 |
| 44+ | 0 | 0 | 1 |
| 45 | 0 | 0 | 1 |
| 45+ | 0 | 0 | 1 |
| 46 | 0 | 0 | 1 |
| 46+ | 0 | 0 | 1 |
| 47 | 0 | 0 | 1 |
| 47+ | 0 | 0 | 1 |
| 48 | 0 | 0 | 1 |
| 48+ | 0 | 0 | 1 |
| 49 | 0 | 0 | 1 |
| 49+ | 0 | 0 | 1 |
| 50 | 0 | 0 | 1 |
| 50+ | 0 | 0 | 1 |
| 51 | 0 | 0 | 1 |
| 51+ | 0 | 0 | 1 |
| 52 | 0 | 0 | 1 |
| 52+ | 0 | 0 | 1 |
| 53 | 0 | 0 | 1 |
| 53+ | 0 | 0 | 1 |
| 54 | 0 | 0 | 1 |
| 54+ | 0 | 0 | 1 |
| 55 | 0 | 0 | 1 |
| 55+ | 0 | 0 | 1 |
| 56 | 0 | 0 | 1 |
| 56+ | 0 | 0 | 1 |
| 57 | 0 | 0 | 1 |
| 57+ | 0 | 1 | 1 |
| 58 | 0 | 1 | 0 |
| 58+ | 1 | 0 | 0 |
| 59 | 1 | 0 | 0 |
| 59+ | 1 | 0 | 0 |
| 60 | 1 | 0 | 0 |
| 60+ | 1 | 0 | 0 |
| 61 | 1 | 0 | 0 |
| 61+ | 1 | 0 | 0 |
| 62 | 1 | 0 | 0 |
| 62+ | 1 | 0 | 0 |
| 63 | 1 | 0 | 0 |
| 63+ | 1 | 0 | 0 |
| 64 | 1 | 0 | 0 |
| 64+ | 1 | 0 | 0 |
| 65 | 1 | 0 | 0 |
| 65+ | 1 | 0 | 0 |
| 66 | 1 | 0 | 0 |
| 66+ | 1 | 0 | 0 |
| 67 | 1 | 0 | 0 |
| 67+ | 1 | 0 | 0 |
| 68 | 1 | 0 | 0 |
| 68+ | 1 | 0 | 0 |
| 69 | 1 | 0 | 0 |
| 69+ | 1 | 0 | 0 |
| 70 | 1 | 0 | 0 |
| 70+ | 1 | 0 | 0 |
| 71 | 1 | 0 | 0 |
| 71+ | 1 | 0 | 0 |
| 72 | 1 | 0 | 0 |
| 72+ | 1 | 0 | 0 |
| 73 | 1 | 0 | 0 |
| 73+ | 1 | 0 | 0 |
| 74 | 1 | 0 | 0 |
| 74+ | 1 | 0 | 0 |
| 75 | 1 | 0 | 0 |
| 75+ | 1 | 0 | 0 |
| 76 | 1 | 0 | 0 |
| 76+ | 1 | 0 | 0 |
| 77 | 1 | 0 | 0 |
| 77+ | 1 | 0 | 0 |
| 78 | 1 | 0 | 0 |
| 78+ | 1 | 0 | 0 |
| 79 | 1 | 0 | 0 |
| 79+ | 1 | 0 | 0 |
| 80 | 1 | 0 | 0 |
| 80+ | 1 | 0 | 0 |
| 81 | 1 | 0 | 0 |
| 81+ | 1 | 0 | 0 |
| 82 | 1 | 0 | 0 |
| 82+ | 1 | 0 | 0 |
| 83 | 1 | 0 | 0 |
| 83+ | 1 | 0 | 0 |
| 84 | 1 | 0 | 0 |
| 84+ | 1 | 0 | 0 |
| 85 | 1 | 0 | 0 |
| 85+ | 1 | 0 | 0 |
| 86 | 1 | 0 | 0 |
| 86+ | 1 | 0 | 0 |
| 87 | 1 | 0 | 0 |
| 87+ | 1 | 0 | 0 |
| 88 | 1 | 0 | 0 |
| 88+ | 1 | 0 | 0 |
| 89 | 1 | 0 | 0 |
| 89+ | 1 | 0 | 0 |
| 90 | 1 | 0 | 0 |
| 90+ | 1 | 0 | 0 |
| 91 | 1 | 0 | 0 |
| 91+ | 1 | 0 | 0 |
| 92 | 1 | 0 | 0 |
| 92+ | 1 | 0 | 0 |
| 93 | 1 | 0 | 0 |
| 93+ | 1 | 0 | 0 |
| 94 | 1 | 0 | 0 |
| 94+ | 1 | 0 | 0 |
| 95 | 1 | 0 | 0 |
| 95+ | 1 | 0 | 0 |
| 96 | 1 | 0 | 0 |
| 96+ | 1 | 0 | 0 |
| 97 | 1 | 0 | 0 |
| 97+ | 1 | 0 | 0 |
| 98 | 1 | 0 | 0 |
| 98+ | 1 | 0 | 0 |
| 99 | 1 | 0 | 0 |
| 99+ | 1 | 0 | 0 |
| 100 | 1 | 0 | 0 |
| 100+ | 1 | 0 | 0 |
| 101 | 1 | 0 | 0 |
| 101+ | 1 | 0 | 0 |
| 102 | 1 | 0 | 0 |
| 102+ | 1 | 0 | 0 |
| 103 | 1 | 0 | 0 |
| 103+ | 1 | 0 | 0 |
| 104 | 1 | 0 | 0 |
| 104+ | 1 | 0 | 0 |
| 105 | 1 | 0 | 0 |
| 105+ | 1 | 0 | 0 |
| 106 | 1 | 0 | 0 |
| 106+ | 1 | 0 | 0 |
| 107 | 1 | 0 | 0 |

19
projects/03/a/Bit.hdl Normal file
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@@ -0,0 +1,19 @@
// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/03/a/Bit.hdl
/**
* 1-bit register:
* If load[t] == 1 then out[t+1] = in[t]
* else out does not change (out[t+1] = out[t])
*/
CHIP Bit {
IN in, load;
OUT out;
PARTS:
Mux(a=mux, b=in, sel=load, out=dff);
DFF(in=dff, out=mux, out=out);
}

865
projects/03/a/Bit.tst Normal file
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@@ -0,0 +1,865 @@
// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/03/a/Bit.tst
load Bit.hdl,
output-file Bit.out,
compare-to Bit.cmp,
output-list time%S1.4.1 in%B2.1.2 load%B2.1.2 out%B2.1.2;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 1,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 1,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 1,
tick,
output;
tock,
output;
set in 1,
set load 1,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 1,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;
set in 1,
set load 0,
tick,
output;
tock,
output;

31
projects/03/a/PC.cmp Normal file
View File

@@ -0,0 +1,31 @@
| time | in |reset|load | inc | out |
| 0+ | 0 | 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 0 | 0 | 0 |
| 1+ | 0 | 0 | 0 | 1 | 0 |
| 2 | 0 | 0 | 0 | 1 | 1 |
| 2+ | -32123 | 0 | 0 | 1 | 1 |
| 3 | -32123 | 0 | 0 | 1 | 2 |
| 3+ | -32123 | 0 | 1 | 1 | 2 |
| 4 | -32123 | 0 | 1 | 1 | -32123 |
| 4+ | -32123 | 0 | 0 | 1 | -32123 |
| 5 | -32123 | 0 | 0 | 1 | -32122 |
| 5+ | -32123 | 0 | 0 | 1 | -32122 |
| 6 | -32123 | 0 | 0 | 1 | -32121 |
| 6+ | 12345 | 0 | 1 | 0 | -32121 |
| 7 | 12345 | 0 | 1 | 0 | 12345 |
| 7+ | 12345 | 1 | 1 | 0 | 12345 |
| 8 | 12345 | 1 | 1 | 0 | 0 |
| 8+ | 12345 | 0 | 1 | 1 | 0 |
| 9 | 12345 | 0 | 1 | 1 | 12345 |
| 9+ | 12345 | 1 | 1 | 1 | 12345 |
| 10 | 12345 | 1 | 1 | 1 | 0 |
| 10+ | 12345 | 0 | 0 | 1 | 0 |
| 11 | 12345 | 0 | 0 | 1 | 1 |
| 11+ | 12345 | 1 | 0 | 1 | 1 |
| 12 | 12345 | 1 | 0 | 1 | 0 |
| 12+ | 0 | 0 | 1 | 1 | 0 |
| 13 | 0 | 0 | 1 | 1 | 0 |
| 13+ | 0 | 0 | 0 | 1 | 0 |
| 14 | 0 | 0 | 0 | 1 | 1 |
| 14+ | 22222 | 1 | 0 | 0 | 1 |
| 15 | 22222 | 1 | 0 | 0 | 0 |

29
projects/03/a/PC.hdl Normal file
View File

@@ -0,0 +1,29 @@
// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/03/a/PC.hdl
/**
* A 16-bit counter with load and reset control bits.
* if (reset[t] == 1) out[t+1] = 0
* else if (load[t] == 1) out[t+1] = in[t]
* else if (inc[t] == 1) out[t+1] = out[t] + 1 (integer addition)
* else out[t+1] = out[t]
*/
CHIP PC {
IN in[16],load,inc,reset;
OUT out[16];
PARTS:
Inc16(in=regout, out=reginc);
Mux16(a=regout, b=reginc, sel=inc, out=incmux);
Mux16(a=incmux, b=in, sel=load, out=loadmux);
Mux16(a=loadmux, b=false, sel=reset, out=resmux);
Or8Way(in[0]=reset, in[1]=load, in[2]=inc, out=regload);
Register(in=resmux, load=regload, out=regout, out=out);
}

125
projects/03/a/PC.tst Normal file
View File

@@ -0,0 +1,125 @@
// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/03/a/PC.tst
load PC.hdl,
output-file PC.out,
compare-to PC.cmp,
output-list time%S1.4.1 in%D1.6.1 reset%B2.1.2 load%B2.1.2 inc%B2.1.2 out%D1.6.1;
set in 0,
set reset 0,
set load 0,
set inc 0,
tick,
output;
tock,
output;
set inc 1,
tick,
output;
tock,
output;
set in -32123,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set load 0,
tick,
output;
tock,
output;
tick,
output;
tock,
output;
set in 12345,
set load 1,
set inc 0,
tick,
output;
tock,
output;
set reset 1,
tick,
output;
tock,
output;
set reset 0,
set inc 1,
tick,
output;
tock,
output;
set reset 1,
tick,
output;
tock,
output;
set reset 0,
set load 0,
tick,
output;
tock,
output;
set reset 1,
tick,
output;
tock,
output;
set in 0,
set reset 0,
set load 1,
tick,
output;
tock,
output;
set load 0,
set inc 1,
tick,
output;
tock,
output;
set in 22222,
set reset 1,
set inc 0,
tick,
output;
tock,
output;

320
projects/03/a/RAM64.cmp Normal file
View File

@@ -0,0 +1,320 @@
| time | in |load |address| out |
| 0+ | 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 0 | 0 |
| 1+ | 0 | 1 | 0 | 0 |
| 2 | 0 | 1 | 0 | 0 |
| 2+ | 1313 | 0 | 0 | 0 |
| 3 | 1313 | 0 | 0 | 0 |
| 3+ | 1313 | 1 | 13 | 0 |
| 4 | 1313 | 1 | 13 | 1313 |
| 4+ | 1313 | 0 | 0 | 0 |
| 5 | 1313 | 0 | 0 | 0 |
| 5+ | 4747 | 0 | 47 | 0 |
| 6 | 4747 | 0 | 47 | 0 |
| 6+ | 4747 | 1 | 47 | 0 |
| 7 | 4747 | 1 | 47 | 4747 |
| 7+ | 4747 | 0 | 47 | 4747 |
| 8 | 4747 | 0 | 47 | 4747 |
| 8 | 4747 | 0 | 13 | 1313 |
| 8+ | 6363 | 0 | 13 | 1313 |
| 9 | 6363 | 0 | 13 | 1313 |
| 9+ | 6363 | 1 | 63 | 0 |
| 10 | 6363 | 1 | 63 | 6363 |
| 10+ | 6363 | 0 | 63 | 6363 |
| 11 | 6363 | 0 | 63 | 6363 |
| 11 | 6363 | 0 | 47 | 4747 |
| 11 | 6363 | 0 | 63 | 6363 |
| 11+ | 6363 | 0 | 40 | 0 |
| 12 | 6363 | 0 | 40 | 0 |
| 12 | 6363 | 0 | 41 | 0 |
| 12 | 6363 | 0 | 42 | 0 |
| 12 | 6363 | 0 | 43 | 0 |
| 12 | 6363 | 0 | 44 | 0 |
| 12 | 6363 | 0 | 45 | 0 |
| 12 | 6363 | 0 | 46 | 0 |
| 12 | 6363 | 0 | 47 | 4747 |
| 12+ | 21845 | 1 | 40 | 0 |
| 13 | 21845 | 1 | 40 | 21845 |
| 13+ | 21845 | 1 | 41 | 0 |
| 14 | 21845 | 1 | 41 | 21845 |
| 14+ | 21845 | 1 | 42 | 0 |
| 15 | 21845 | 1 | 42 | 21845 |
| 15+ | 21845 | 1 | 43 | 0 |
| 16 | 21845 | 1 | 43 | 21845 |
| 16+ | 21845 | 1 | 44 | 0 |
| 17 | 21845 | 1 | 44 | 21845 |
| 17+ | 21845 | 1 | 45 | 0 |
| 18 | 21845 | 1 | 45 | 21845 |
| 18+ | 21845 | 1 | 46 | 0 |
| 19 | 21845 | 1 | 46 | 21845 |
| 19+ | 21845 | 1 | 47 | 4747 |
| 20 | 21845 | 1 | 47 | 21845 |
| 20+ | 21845 | 0 | 40 | 21845 |
| 21 | 21845 | 0 | 40 | 21845 |
| 21 | 21845 | 0 | 41 | 21845 |
| 21 | 21845 | 0 | 42 | 21845 |
| 21 | 21845 | 0 | 43 | 21845 |
| 21 | 21845 | 0 | 44 | 21845 |
| 21 | 21845 | 0 | 45 | 21845 |
| 21 | 21845 | 0 | 46 | 21845 |
| 21 | 21845 | 0 | 47 | 21845 |
| 21+ | -21846 | 1 | 40 | 21845 |
| 22 | -21846 | 1 | 40 | -21846 |
| 22+ | -21846 | 0 | 40 | -21846 |
| 23 | -21846 | 0 | 40 | -21846 |
| 23 | -21846 | 0 | 41 | 21845 |
| 23 | -21846 | 0 | 42 | 21845 |
| 23 | -21846 | 0 | 43 | 21845 |
| 23 | -21846 | 0 | 44 | 21845 |
| 23 | -21846 | 0 | 45 | 21845 |
| 23 | -21846 | 0 | 46 | 21845 |
| 23 | -21846 | 0 | 47 | 21845 |
| 23+ | 21845 | 1 | 40 | -21846 |
| 24 | 21845 | 1 | 40 | 21845 |
| 24+ | -21846 | 1 | 41 | 21845 |
| 25 | -21846 | 1 | 41 | -21846 |
| 25+ | -21846 | 0 | 40 | 21845 |
| 26 | -21846 | 0 | 40 | 21845 |
| 26 | -21846 | 0 | 41 | -21846 |
| 26 | -21846 | 0 | 42 | 21845 |
| 26 | -21846 | 0 | 43 | 21845 |
| 26 | -21846 | 0 | 44 | 21845 |
| 26 | -21846 | 0 | 45 | 21845 |
| 26 | -21846 | 0 | 46 | 21845 |
| 26 | -21846 | 0 | 47 | 21845 |
| 26+ | 21845 | 1 | 41 | -21846 |
| 27 | 21845 | 1 | 41 | 21845 |
| 27+ | -21846 | 1 | 42 | 21845 |
| 28 | -21846 | 1 | 42 | -21846 |
| 28+ | -21846 | 0 | 40 | 21845 |
| 29 | -21846 | 0 | 40 | 21845 |
| 29 | -21846 | 0 | 41 | 21845 |
| 29 | -21846 | 0 | 42 | -21846 |
| 29 | -21846 | 0 | 43 | 21845 |
| 29 | -21846 | 0 | 44 | 21845 |
| 29 | -21846 | 0 | 45 | 21845 |
| 29 | -21846 | 0 | 46 | 21845 |
| 29 | -21846 | 0 | 47 | 21845 |
| 29+ | 21845 | 1 | 42 | -21846 |
| 30 | 21845 | 1 | 42 | 21845 |
| 30+ | -21846 | 1 | 43 | 21845 |
| 31 | -21846 | 1 | 43 | -21846 |
| 31+ | -21846 | 0 | 40 | 21845 |
| 32 | -21846 | 0 | 40 | 21845 |
| 32 | -21846 | 0 | 41 | 21845 |
| 32 | -21846 | 0 | 42 | 21845 |
| 32 | -21846 | 0 | 43 | -21846 |
| 32 | -21846 | 0 | 44 | 21845 |
| 32 | -21846 | 0 | 45 | 21845 |
| 32 | -21846 | 0 | 46 | 21845 |
| 32 | -21846 | 0 | 47 | 21845 |
| 32+ | 21845 | 1 | 43 | -21846 |
| 33 | 21845 | 1 | 43 | 21845 |
| 33+ | -21846 | 1 | 44 | 21845 |
| 34 | -21846 | 1 | 44 | -21846 |
| 34+ | -21846 | 0 | 40 | 21845 |
| 35 | -21846 | 0 | 40 | 21845 |
| 35 | -21846 | 0 | 41 | 21845 |
| 35 | -21846 | 0 | 42 | 21845 |
| 35 | -21846 | 0 | 43 | 21845 |
| 35 | -21846 | 0 | 44 | -21846 |
| 35 | -21846 | 0 | 45 | 21845 |
| 35 | -21846 | 0 | 46 | 21845 |
| 35 | -21846 | 0 | 47 | 21845 |
| 35+ | 21845 | 1 | 44 | -21846 |
| 36 | 21845 | 1 | 44 | 21845 |
| 36+ | -21846 | 1 | 45 | 21845 |
| 37 | -21846 | 1 | 45 | -21846 |
| 37+ | -21846 | 0 | 40 | 21845 |
| 38 | -21846 | 0 | 40 | 21845 |
| 38 | -21846 | 0 | 41 | 21845 |
| 38 | -21846 | 0 | 42 | 21845 |
| 38 | -21846 | 0 | 43 | 21845 |
| 38 | -21846 | 0 | 44 | 21845 |
| 38 | -21846 | 0 | 45 | -21846 |
| 38 | -21846 | 0 | 46 | 21845 |
| 38 | -21846 | 0 | 47 | 21845 |
| 38+ | 21845 | 1 | 45 | -21846 |
| 39 | 21845 | 1 | 45 | 21845 |
| 39+ | -21846 | 1 | 46 | 21845 |
| 40 | -21846 | 1 | 46 | -21846 |
| 40+ | -21846 | 0 | 40 | 21845 |
| 41 | -21846 | 0 | 40 | 21845 |
| 41 | -21846 | 0 | 41 | 21845 |
| 41 | -21846 | 0 | 42 | 21845 |
| 41 | -21846 | 0 | 43 | 21845 |
| 41 | -21846 | 0 | 44 | 21845 |
| 41 | -21846 | 0 | 45 | 21845 |
| 41 | -21846 | 0 | 46 | -21846 |
| 41 | -21846 | 0 | 47 | 21845 |
| 41+ | 21845 | 1 | 46 | -21846 |
| 42 | 21845 | 1 | 46 | 21845 |
| 42+ | -21846 | 1 | 47 | 21845 |
| 43 | -21846 | 1 | 47 | -21846 |
| 43+ | -21846 | 0 | 40 | 21845 |
| 44 | -21846 | 0 | 40 | 21845 |
| 44 | -21846 | 0 | 41 | 21845 |
| 44 | -21846 | 0 | 42 | 21845 |
| 44 | -21846 | 0 | 43 | 21845 |
| 44 | -21846 | 0 | 44 | 21845 |
| 44 | -21846 | 0 | 45 | 21845 |
| 44 | -21846 | 0 | 46 | 21845 |
| 44 | -21846 | 0 | 47 | -21846 |
| 44+ | 21845 | 1 | 47 | -21846 |
| 45 | 21845 | 1 | 47 | 21845 |
| 45+ | 21845 | 0 | 40 | 21845 |
| 46 | 21845 | 0 | 40 | 21845 |
| 46 | 21845 | 0 | 41 | 21845 |
| 46 | 21845 | 0 | 42 | 21845 |
| 46 | 21845 | 0 | 43 | 21845 |
| 46 | 21845 | 0 | 44 | 21845 |
| 46 | 21845 | 0 | 45 | 21845 |
| 46 | 21845 | 0 | 46 | 21845 |
| 46 | 21845 | 0 | 47 | 21845 |
| 46+ | 21845 | 0 | 5 | 0 |
| 47 | 21845 | 0 | 5 | 0 |
| 47 | 21845 | 0 | 13 | 1313 |
| 47 | 21845 | 0 | 21 | 0 |
| 47 | 21845 | 0 | 29 | 0 |
| 47 | 21845 | 0 | 37 | 0 |
| 47 | 21845 | 0 | 45 | 21845 |
| 47 | 21845 | 0 | 53 | 0 |
| 47 | 21845 | 0 | 61 | 0 |
| 47+ | 21845 | 1 | 5 | 0 |
| 48 | 21845 | 1 | 5 | 21845 |
| 48+ | 21845 | 1 | 13 | 1313 |
| 49 | 21845 | 1 | 13 | 21845 |
| 49+ | 21845 | 1 | 21 | 0 |
| 50 | 21845 | 1 | 21 | 21845 |
| 50+ | 21845 | 1 | 29 | 0 |
| 51 | 21845 | 1 | 29 | 21845 |
| 51+ | 21845 | 1 | 37 | 0 |
| 52 | 21845 | 1 | 37 | 21845 |
| 52+ | 21845 | 1 | 45 | 21845 |
| 53 | 21845 | 1 | 45 | 21845 |
| 53+ | 21845 | 1 | 53 | 0 |
| 54 | 21845 | 1 | 53 | 21845 |
| 54+ | 21845 | 1 | 61 | 0 |
| 55 | 21845 | 1 | 61 | 21845 |
| 55+ | 21845 | 0 | 5 | 21845 |
| 56 | 21845 | 0 | 5 | 21845 |
| 56 | 21845 | 0 | 13 | 21845 |
| 56 | 21845 | 0 | 21 | 21845 |
| 56 | 21845 | 0 | 29 | 21845 |
| 56 | 21845 | 0 | 37 | 21845 |
| 56 | 21845 | 0 | 45 | 21845 |
| 56 | 21845 | 0 | 53 | 21845 |
| 56 | 21845 | 0 | 61 | 21845 |
| 56+ | -21846 | 1 | 5 | 21845 |
| 57 | -21846 | 1 | 5 | -21846 |
| 57+ | -21846 | 0 | 5 | -21846 |
| 58 | -21846 | 0 | 5 | -21846 |
| 58 | -21846 | 0 | 13 | 21845 |
| 58 | -21846 | 0 | 21 | 21845 |
| 58 | -21846 | 0 | 29 | 21845 |
| 58 | -21846 | 0 | 37 | 21845 |
| 58 | -21846 | 0 | 45 | 21845 |
| 58 | -21846 | 0 | 53 | 21845 |
| 58 | -21846 | 0 | 61 | 21845 |
| 58+ | 21845 | 1 | 5 | -21846 |
| 59 | 21845 | 1 | 5 | 21845 |
| 59+ | -21846 | 1 | 13 | 21845 |
| 60 | -21846 | 1 | 13 | -21846 |
| 60+ | -21846 | 0 | 5 | 21845 |
| 61 | -21846 | 0 | 5 | 21845 |
| 61 | -21846 | 0 | 13 | -21846 |
| 61 | -21846 | 0 | 21 | 21845 |
| 61 | -21846 | 0 | 29 | 21845 |
| 61 | -21846 | 0 | 37 | 21845 |
| 61 | -21846 | 0 | 45 | 21845 |
| 61 | -21846 | 0 | 53 | 21845 |
| 61 | -21846 | 0 | 61 | 21845 |
| 61+ | 21845 | 1 | 13 | -21846 |
| 62 | 21845 | 1 | 13 | 21845 |
| 62+ | -21846 | 1 | 21 | 21845 |
| 63 | -21846 | 1 | 21 | -21846 |
| 63+ | -21846 | 0 | 5 | 21845 |
| 64 | -21846 | 0 | 5 | 21845 |
| 64 | -21846 | 0 | 13 | 21845 |
| 64 | -21846 | 0 | 21 | -21846 |
| 64 | -21846 | 0 | 29 | 21845 |
| 64 | -21846 | 0 | 37 | 21845 |
| 64 | -21846 | 0 | 45 | 21845 |
| 64 | -21846 | 0 | 53 | 21845 |
| 64 | -21846 | 0 | 61 | 21845 |
| 64+ | 21845 | 1 | 21 | -21846 |
| 65 | 21845 | 1 | 21 | 21845 |
| 65+ | -21846 | 1 | 29 | 21845 |
| 66 | -21846 | 1 | 29 | -21846 |
| 66+ | -21846 | 0 | 5 | 21845 |
| 67 | -21846 | 0 | 5 | 21845 |
| 67 | -21846 | 0 | 13 | 21845 |
| 67 | -21846 | 0 | 21 | 21845 |
| 67 | -21846 | 0 | 29 | -21846 |
| 67 | -21846 | 0 | 37 | 21845 |
| 67 | -21846 | 0 | 45 | 21845 |
| 67 | -21846 | 0 | 53 | 21845 |
| 67 | -21846 | 0 | 61 | 21845 |
| 67+ | 21845 | 1 | 29 | -21846 |
| 68 | 21845 | 1 | 29 | 21845 |
| 68+ | -21846 | 1 | 37 | 21845 |
| 69 | -21846 | 1 | 37 | -21846 |
| 69+ | -21846 | 0 | 5 | 21845 |
| 70 | -21846 | 0 | 5 | 21845 |
| 70 | -21846 | 0 | 13 | 21845 |
| 70 | -21846 | 0 | 21 | 21845 |
| 70 | -21846 | 0 | 29 | 21845 |
| 70 | -21846 | 0 | 37 | -21846 |
| 70 | -21846 | 0 | 45 | 21845 |
| 70 | -21846 | 0 | 53 | 21845 |
| 70 | -21846 | 0 | 61 | 21845 |
| 70+ | 21845 | 1 | 37 | -21846 |
| 71 | 21845 | 1 | 37 | 21845 |
| 71+ | -21846 | 1 | 45 | 21845 |
| 72 | -21846 | 1 | 45 | -21846 |
| 72+ | -21846 | 0 | 5 | 21845 |
| 73 | -21846 | 0 | 5 | 21845 |
| 73 | -21846 | 0 | 13 | 21845 |
| 73 | -21846 | 0 | 21 | 21845 |
| 73 | -21846 | 0 | 29 | 21845 |
| 73 | -21846 | 0 | 37 | 21845 |
| 73 | -21846 | 0 | 45 | -21846 |
| 73 | -21846 | 0 | 53 | 21845 |
| 73 | -21846 | 0 | 61 | 21845 |
| 73+ | 21845 | 1 | 45 | -21846 |
| 74 | 21845 | 1 | 45 | 21845 |
| 74+ | -21846 | 1 | 53 | 21845 |
| 75 | -21846 | 1 | 53 | -21846 |
| 75+ | -21846 | 0 | 5 | 21845 |
| 76 | -21846 | 0 | 5 | 21845 |
| 76 | -21846 | 0 | 13 | 21845 |
| 76 | -21846 | 0 | 21 | 21845 |
| 76 | -21846 | 0 | 29 | 21845 |
| 76 | -21846 | 0 | 37 | 21845 |
| 76 | -21846 | 0 | 45 | 21845 |
| 76 | -21846 | 0 | 53 | -21846 |
| 76 | -21846 | 0 | 61 | 21845 |
| 76+ | 21845 | 1 | 53 | -21846 |
| 77 | 21845 | 1 | 53 | 21845 |
| 77+ | -21846 | 1 | 61 | 21845 |
| 78 | -21846 | 1 | 61 | -21846 |
| 78+ | -21846 | 0 | 5 | 21845 |
| 79 | -21846 | 0 | 5 | 21845 |
| 79 | -21846 | 0 | 13 | 21845 |
| 79 | -21846 | 0 | 21 | 21845 |
| 79 | -21846 | 0 | 29 | 21845 |
| 79 | -21846 | 0 | 37 | 21845 |
| 79 | -21846 | 0 | 45 | 21845 |
| 79 | -21846 | 0 | 53 | 21845 |
| 79 | -21846 | 0 | 61 | -21846 |
| 79+ | 21845 | 1 | 61 | -21846 |
| 80 | 21845 | 1 | 61 | 21845 |
| 80+ | 21845 | 0 | 5 | 21845 |
| 81 | 21845 | 0 | 5 | 21845 |
| 81 | 21845 | 0 | 13 | 21845 |
| 81 | 21845 | 0 | 21 | 21845 |
| 81 | 21845 | 0 | 29 | 21845 |
| 81 | 21845 | 0 | 37 | 21845 |
| 81 | 21845 | 0 | 45 | 21845 |
| 81 | 21845 | 0 | 53 | 21845 |
| 81 | 21845 | 0 | 61 | 21845 |

29
projects/03/a/RAM64.hdl Normal file
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@@ -0,0 +1,29 @@
// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/03/a/RAM64.hdl
/**
* Memory of 64 registers, each 16 bit-wide. Out holds the value
* stored at the memory location specified by address. If load==1, then
* the in value is loaded into the memory location specified by address
* (the loaded value will be emitted to out from the next time step onward).
*/
CHIP RAM64 {
IN in[16], load, address[6];
OUT out[16];
PARTS:
RAM8(in=in, load=load1, address=address[0..2], out=out1);
RAM8(in=in, load=load2, address=address[0..2], out=out2);
RAM8(in=in, load=load3, address=address[0..2], out=out3);
RAM8(in=in, load=load4, address=address[0..2], out=out4);
RAM8(in=in, load=load5, address=address[0..2], out=out5);
RAM8(in=in, load=load6, address=address[0..2], out=out6);
RAM8(in=in, load=load7, address=address[0..2], out=out7);
RAM8(in=in, load=load8, address=address[0..2], out=out8);
DMux8Way(in=load, sel=address[3..5], a=load1, b=load2, c=load3, d=load4, e=load5, f=load6, g=load7, h=load8);
Mux8Way16(a=out1, b=out2, c=out3, d=out4, e=out5, f=out6, g=out7, h=out8, sel=address[3..5], out=out);
}

1026
projects/03/a/RAM64.tst Normal file
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File diff suppressed because it is too large Load Diff

173
projects/03/a/RAM8.cmp Normal file
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@@ -0,0 +1,173 @@
| time | in |load |address| out |
| 0+ | 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 0 | 0 |
| 1+ | 0 | 1 | 0 | 0 |
| 2 | 0 | 1 | 0 | 0 |
| 2+ | 11111 | 0 | 0 | 0 |
| 3 | 11111 | 0 | 0 | 0 |
| 3+ | 11111 | 1 | 1 | 0 |
| 4 | 11111 | 1 | 1 | 11111 |
| 4+ | 11111 | 0 | 0 | 0 |
| 5 | 11111 | 0 | 0 | 0 |
| 5+ | 3333 | 0 | 3 | 0 |
| 6 | 3333 | 0 | 3 | 0 |
| 6+ | 3333 | 1 | 3 | 0 |
| 7 | 3333 | 1 | 3 | 3333 |
| 7+ | 3333 | 0 | 3 | 3333 |
| 8 | 3333 | 0 | 3 | 3333 |
| 8 | 3333 | 0 | 1 | 11111 |
| 8+ | 7777 | 0 | 1 | 11111 |
| 9 | 7777 | 0 | 1 | 11111 |
| 9+ | 7777 | 1 | 7 | 0 |
| 10 | 7777 | 1 | 7 | 7777 |
| 10+ | 7777 | 0 | 7 | 7777 |
| 11 | 7777 | 0 | 7 | 7777 |
| 11 | 7777 | 0 | 3 | 3333 |
| 11 | 7777 | 0 | 7 | 7777 |
| 11+ | 7777 | 0 | 0 | 0 |
| 12 | 7777 | 0 | 0 | 0 |
| 12 | 7777 | 0 | 1 | 11111 |
| 12 | 7777 | 0 | 2 | 0 |
| 12 | 7777 | 0 | 3 | 3333 |
| 12 | 7777 | 0 | 4 | 0 |
| 12 | 7777 | 0 | 5 | 0 |
| 12 | 7777 | 0 | 6 | 0 |
| 12 | 7777 | 0 | 7 | 7777 |
| 12+ | 21845 | 1 | 0 | 0 |
| 13 | 21845 | 1 | 0 | 21845 |
| 13+ | 21845 | 1 | 1 | 11111 |
| 14 | 21845 | 1 | 1 | 21845 |
| 14+ | 21845 | 1 | 2 | 0 |
| 15 | 21845 | 1 | 2 | 21845 |
| 15+ | 21845 | 1 | 3 | 3333 |
| 16 | 21845 | 1 | 3 | 21845 |
| 16+ | 21845 | 1 | 4 | 0 |
| 17 | 21845 | 1 | 4 | 21845 |
| 17+ | 21845 | 1 | 5 | 0 |
| 18 | 21845 | 1 | 5 | 21845 |
| 18+ | 21845 | 1 | 6 | 0 |
| 19 | 21845 | 1 | 6 | 21845 |
| 19+ | 21845 | 1 | 7 | 7777 |
| 20 | 21845 | 1 | 7 | 21845 |
| 20+ | 21845 | 0 | 0 | 21845 |
| 21 | 21845 | 0 | 0 | 21845 |
| 21 | 21845 | 0 | 1 | 21845 |
| 21 | 21845 | 0 | 2 | 21845 |
| 21 | 21845 | 0 | 3 | 21845 |
| 21 | 21845 | 0 | 4 | 21845 |
| 21 | 21845 | 0 | 5 | 21845 |
| 21 | 21845 | 0 | 6 | 21845 |
| 21 | 21845 | 0 | 7 | 21845 |
| 21+ | -21846 | 1 | 0 | 21845 |
| 22 | -21846 | 1 | 0 | -21846 |
| 22+ | -21846 | 0 | 0 | -21846 |
| 23 | -21846 | 0 | 0 | -21846 |
| 23 | -21846 | 0 | 1 | 21845 |
| 23 | -21846 | 0 | 2 | 21845 |
| 23 | -21846 | 0 | 3 | 21845 |
| 23 | -21846 | 0 | 4 | 21845 |
| 23 | -21846 | 0 | 5 | 21845 |
| 23 | -21846 | 0 | 6 | 21845 |
| 23 | -21846 | 0 | 7 | 21845 |
| 23+ | 21845 | 1 | 0 | -21846 |
| 24 | 21845 | 1 | 0 | 21845 |
| 24+ | -21846 | 1 | 1 | 21845 |
| 25 | -21846 | 1 | 1 | -21846 |
| 25+ | -21846 | 0 | 0 | 21845 |
| 26 | -21846 | 0 | 0 | 21845 |
| 26 | -21846 | 0 | 1 | -21846 |
| 26 | -21846 | 0 | 2 | 21845 |
| 26 | -21846 | 0 | 3 | 21845 |
| 26 | -21846 | 0 | 4 | 21845 |
| 26 | -21846 | 0 | 5 | 21845 |
| 26 | -21846 | 0 | 6 | 21845 |
| 26 | -21846 | 0 | 7 | 21845 |
| 26+ | 21845 | 1 | 1 | -21846 |
| 27 | 21845 | 1 | 1 | 21845 |
| 27+ | -21846 | 1 | 2 | 21845 |
| 28 | -21846 | 1 | 2 | -21846 |
| 28+ | -21846 | 0 | 0 | 21845 |
| 29 | -21846 | 0 | 0 | 21845 |
| 29 | -21846 | 0 | 1 | 21845 |
| 29 | -21846 | 0 | 2 | -21846 |
| 29 | -21846 | 0 | 3 | 21845 |
| 29 | -21846 | 0 | 4 | 21845 |
| 29 | -21846 | 0 | 5 | 21845 |
| 29 | -21846 | 0 | 6 | 21845 |
| 29 | -21846 | 0 | 7 | 21845 |
| 29+ | 21845 | 1 | 2 | -21846 |
| 30 | 21845 | 1 | 2 | 21845 |
| 30+ | -21846 | 1 | 3 | 21845 |
| 31 | -21846 | 1 | 3 | -21846 |
| 31+ | -21846 | 0 | 0 | 21845 |
| 32 | -21846 | 0 | 0 | 21845 |
| 32 | -21846 | 0 | 1 | 21845 |
| 32 | -21846 | 0 | 2 | 21845 |
| 32 | -21846 | 0 | 3 | -21846 |
| 32 | -21846 | 0 | 4 | 21845 |
| 32 | -21846 | 0 | 5 | 21845 |
| 32 | -21846 | 0 | 6 | 21845 |
| 32 | -21846 | 0 | 7 | 21845 |
| 32+ | 21845 | 1 | 3 | -21846 |
| 33 | 21845 | 1 | 3 | 21845 |
| 33+ | -21846 | 1 | 4 | 21845 |
| 34 | -21846 | 1 | 4 | -21846 |
| 34+ | -21846 | 0 | 0 | 21845 |
| 35 | -21846 | 0 | 0 | 21845 |
| 35 | -21846 | 0 | 1 | 21845 |
| 35 | -21846 | 0 | 2 | 21845 |
| 35 | -21846 | 0 | 3 | 21845 |
| 35 | -21846 | 0 | 4 | -21846 |
| 35 | -21846 | 0 | 5 | 21845 |
| 35 | -21846 | 0 | 6 | 21845 |
| 35 | -21846 | 0 | 7 | 21845 |
| 35+ | 21845 | 1 | 4 | -21846 |
| 36 | 21845 | 1 | 4 | 21845 |
| 36+ | -21846 | 1 | 5 | 21845 |
| 37 | -21846 | 1 | 5 | -21846 |
| 37+ | -21846 | 0 | 0 | 21845 |
| 38 | -21846 | 0 | 0 | 21845 |
| 38 | -21846 | 0 | 1 | 21845 |
| 38 | -21846 | 0 | 2 | 21845 |
| 38 | -21846 | 0 | 3 | 21845 |
| 38 | -21846 | 0 | 4 | 21845 |
| 38 | -21846 | 0 | 5 | -21846 |
| 38 | -21846 | 0 | 6 | 21845 |
| 38 | -21846 | 0 | 7 | 21845 |
| 38+ | 21845 | 1 | 5 | -21846 |
| 39 | 21845 | 1 | 5 | 21845 |
| 39+ | -21846 | 1 | 6 | 21845 |
| 40 | -21846 | 1 | 6 | -21846 |
| 40+ | -21846 | 0 | 0 | 21845 |
| 41 | -21846 | 0 | 0 | 21845 |
| 41 | -21846 | 0 | 1 | 21845 |
| 41 | -21846 | 0 | 2 | 21845 |
| 41 | -21846 | 0 | 3 | 21845 |
| 41 | -21846 | 0 | 4 | 21845 |
| 41 | -21846 | 0 | 5 | 21845 |
| 41 | -21846 | 0 | 6 | -21846 |
| 41 | -21846 | 0 | 7 | 21845 |
| 41+ | 21845 | 1 | 6 | -21846 |
| 42 | 21845 | 1 | 6 | 21845 |
| 42+ | -21846 | 1 | 7 | 21845 |
| 43 | -21846 | 1 | 7 | -21846 |
| 43+ | -21846 | 0 | 0 | 21845 |
| 44 | -21846 | 0 | 0 | 21845 |
| 44 | -21846 | 0 | 1 | 21845 |
| 44 | -21846 | 0 | 2 | 21845 |
| 44 | -21846 | 0 | 3 | 21845 |
| 44 | -21846 | 0 | 4 | 21845 |
| 44 | -21846 | 0 | 5 | 21845 |
| 44 | -21846 | 0 | 6 | 21845 |
| 44 | -21846 | 0 | 7 | -21846 |
| 44+ | 21845 | 1 | 7 | -21846 |
| 45 | 21845 | 1 | 7 | 21845 |
| 45+ | 21845 | 0 | 0 | 21845 |
| 46 | 21845 | 0 | 0 | 21845 |
| 46 | 21845 | 0 | 1 | 21845 |
| 46 | 21845 | 0 | 2 | 21845 |
| 46 | 21845 | 0 | 3 | 21845 |
| 46 | 21845 | 0 | 4 | 21845 |
| 46 | 21845 | 0 | 5 | 21845 |
| 46 | 21845 | 0 | 6 | 21845 |
| 46 | 21845 | 0 | 7 | 21845 |

29
projects/03/a/RAM8.hdl Normal file
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@@ -0,0 +1,29 @@
// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/03/a/RAM8.hdl
/**
* Memory of 8 registers, each 16 bit-wide. Out holds the value
* stored at the memory location specified by address. If load==1, then
* the in value is loaded into the memory location specified by address
* (the loaded value will be emitted to out from the next time step onward).
*/
CHIP RAM8 {
IN in[16], load, address[3];
OUT out[16];
PARTS:
Register(in=in, load=reg0l, out=reg0);
Register(in=in, load=reg1l, out=reg1);
Register(in=in, load=reg2l, out=reg2);
Register(in=in, load=reg3l, out=reg3);
Register(in=in, load=reg4l, out=reg4);
Register(in=in, load=reg5l, out=reg5);
Register(in=in, load=reg6l, out=reg6);
Register(in=in, load=reg7l, out=reg7);
DMux8Way(in=load, sel=address, a=reg0l, b=reg1l, c=reg2l, d=reg3l, e=reg4l, f=reg5l, g=reg6l, h=reg7l);
Mux8Way16(a=reg0, b=reg1, c=reg2, d=reg3, e=reg4, f=reg5, g=reg6, h=reg7, sel=address, out=out);
}

560
projects/03/a/RAM8.tst Normal file
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@@ -0,0 +1,560 @@
// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/03/a/RAM8.tst
load RAM8.hdl,
output-file RAM8.out,
compare-to RAM8.cmp,
output-list time%S1.4.1 in%D1.6.1 load%B2.1.2 address%D3.1.3 out%D1.6.1;
set in 0,
set load 0,
set address 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in 11111,
set load 0,
tick,
output;
tock,
output;
set load 1,
set address 1,
tick,
output;
tock,
output;
set load 0,
set address 0,
tick,
output;
tock,
output;
set in 3333,
set address 3,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set load 0,
tick,
output;
tock,
output;
set address 1,
eval,
output;
set in 7777,
tick,
output;
tock,
output;
set load 1,
set address 7,
tick,
output;
tock,
output;
set load 0,
tick,
output;
tock,
output;
set address 3,
eval,
output;
set address 7,
eval,
output;
set load 0,
set address 0,
tick,
output;
tock,
output;
set address 1,
eval,
output;
set address 2,
eval,
output;
set address 3,
eval,
output;
set address 4,
eval,
output;
set address 5,
eval,
output;
set address 6,
eval,
output;
set address 7,
eval,
output;
set load 1,
set in %B0101010101010101,
set address 0,
tick,
output;
tock,
output;
set address 1,
tick,
output,
tock,
output;
set address 2,
tick,
output,
tock,
output;
set address 3,
tick,
output,
tock,
output;
set address 4,
tick,
output,
tock,
output;
set address 5,
tick,
output,
tock,
output;
set address 6,
tick,
output,
tock,
output;
set address 7,
tick,
output,
tock,
output;
set load 0,
set address 0,
tick,
output;
tock,
output;
set address 1,
eval,
output;
set address 2,
eval,
output;
set address 3,
eval,
output;
set address 4,
eval,
output;
set address 5,
eval,
output;
set address 6,
eval,
output;
set address 7,
eval,
output;
set load 1,
set address 0,
set in %B1010101010101010,
tick,
output;
tock,
output;
set load 0,
set address 0,
tick,
output;
tock,
output;
set address 1,
eval,
output;
set address 2,
eval,
output;
set address 3,
eval,
output;
set address 4,
eval,
output;
set address 5,
eval,
output;
set address 6,
eval,
output;
set address 7,
eval,
output;
set load 1,
set address 0,
set in %B0101010101010101,
tick,
output,
tock,
output;
set address 1,
set in %B1010101010101010,
tick,
output;
tock,
output;
set load 0,
set address 0,
tick,
output;
tock,
output;
set address 1,
eval,
output;
set address 2,
eval,
output;
set address 3,
eval,
output;
set address 4,
eval,
output;
set address 5,
eval,
output;
set address 6,
eval,
output;
set address 7,
eval,
output;
set load 1,
set address 1,
set in %B0101010101010101,
tick,
output,
tock,
output;
set address 2,
set in %B1010101010101010,
tick,
output;
tock,
output;
set load 0,
set address 0,
tick,
output;
tock,
output;
set address 1,
eval,
output;
set address 2,
eval,
output;
set address 3,
eval,
output;
set address 4,
eval,
output;
set address 5,
eval,
output;
set address 6,
eval,
output;
set address 7,
eval,
output;
set load 1,
set address 2,
set in %B0101010101010101,
tick,
output,
tock,
output;
set address 3,
set in %B1010101010101010,
tick,
output;
tock,
output;
set load 0,
set address 0,
tick,
output;
tock,
output;
set address 1,
eval,
output;
set address 2,
eval,
output;
set address 3,
eval,
output;
set address 4,
eval,
output;
set address 5,
eval,
output;
set address 6,
eval,
output;
set address 7,
eval,
output;
set load 1,
set address 3,
set in %B0101010101010101,
tick,
output,
tock,
output;
set address 4,
set in %B1010101010101010,
tick,
output;
tock,
output;
set load 0,
set address 0,
tick,
output;
tock,
output;
set address 1,
eval,
output;
set address 2,
eval,
output;
set address 3,
eval,
output;
set address 4,
eval,
output;
set address 5,
eval,
output;
set address 6,
eval,
output;
set address 7,
eval,
output;
set load 1,
set address 4,
set in %B0101010101010101,
tick,
output,
tock,
output;
set address 5,
set in %B1010101010101010,
tick,
output;
tock,
output;
set load 0,
set address 0,
tick,
output;
tock,
output;
set address 1,
eval,
output;
set address 2,
eval,
output;
set address 3,
eval,
output;
set address 4,
eval,
output;
set address 5,
eval,
output;
set address 6,
eval,
output;
set address 7,
eval,
output;
set load 1,
set address 5,
set in %B0101010101010101,
tick,
output,
tock,
output;
set address 6,
set in %B1010101010101010,
tick,
output;
tock,
output;
set load 0,
set address 0,
tick,
output;
tock,
output;
set address 1,
eval,
output;
set address 2,
eval,
output;
set address 3,
eval,
output;
set address 4,
eval,
output;
set address 5,
eval,
output;
set address 6,
eval,
output;
set address 7,
eval,
output;
set load 1,
set address 6,
set in %B0101010101010101,
tick,
output,
tock,
output;
set address 7,
set in %B1010101010101010,
tick,
output;
tock,
output;
set load 0,
set address 0,
tick,
output;
tock,
output;
set address 1,
eval,
output;
set address 2,
eval,
output;
set address 3,
eval,
output;
set address 4,
eval,
output;
set address 5,
eval,
output;
set address 6,
eval,
output;
set address 7,
eval,
output;
set load 1,
set address 7,
set in %B0101010101010101,
tick,
output,
tock,
output;
set load 0,
set address 0,
tick,
output;
tock,
output;
set address 1,
eval,
output;
set address 2,
eval,
output;
set address 3,
eval,
output;
set address 4,
eval,
output;
set address 5,
eval,
output;
set address 6,
eval,
output;
set address 7,
eval,
output;

149
projects/03/a/Register.cmp Normal file
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@@ -0,0 +1,149 @@
| time | in |load | out |
| 0+ | 0 | 0 | 0 |
| 1 | 0 | 0 | 0 |
| 1+ | 0 | 1 | 0 |
| 2 | 0 | 1 | 0 |
| 2+ | -32123 | 0 | 0 |
| 3 | -32123 | 0 | 0 |
| 3+ | 11111 | 0 | 0 |
| 4 | 11111 | 0 | 0 |
| 4+ | -32123 | 1 | 0 |
| 5 | -32123 | 1 | -32123 |
| 5+ | -32123 | 1 | -32123 |
| 6 | -32123 | 1 | -32123 |
| 6+ | -32123 | 0 | -32123 |
| 7 | -32123 | 0 | -32123 |
| 7+ | 12345 | 1 | -32123 |
| 8 | 12345 | 1 | 12345 |
| 8+ | 0 | 0 | 12345 |
| 9 | 0 | 0 | 12345 |
| 9+ | 0 | 1 | 12345 |
| 10 | 0 | 1 | 0 |
| 10+ | 1 | 0 | 0 |
| 11 | 1 | 0 | 0 |
| 11+ | 1 | 1 | 0 |
| 12 | 1 | 1 | 1 |
| 12+ | 2 | 0 | 1 |
| 13 | 2 | 0 | 1 |
| 13+ | 2 | 1 | 1 |
| 14 | 2 | 1 | 2 |
| 14+ | 4 | 0 | 2 |
| 15 | 4 | 0 | 2 |
| 15+ | 4 | 1 | 2 |
| 16 | 4 | 1 | 4 |
| 16+ | 8 | 0 | 4 |
| 17 | 8 | 0 | 4 |
| 17+ | 8 | 1 | 4 |
| 18 | 8 | 1 | 8 |
| 18+ | 16 | 0 | 8 |
| 19 | 16 | 0 | 8 |
| 19+ | 16 | 1 | 8 |
| 20 | 16 | 1 | 16 |
| 20+ | 32 | 0 | 16 |
| 21 | 32 | 0 | 16 |
| 21+ | 32 | 1 | 16 |
| 22 | 32 | 1 | 32 |
| 22+ | 64 | 0 | 32 |
| 23 | 64 | 0 | 32 |
| 23+ | 64 | 1 | 32 |
| 24 | 64 | 1 | 64 |
| 24+ | 128 | 0 | 64 |
| 25 | 128 | 0 | 64 |
| 25+ | 128 | 1 | 64 |
| 26 | 128 | 1 | 128 |
| 26+ | 256 | 0 | 128 |
| 27 | 256 | 0 | 128 |
| 27+ | 256 | 1 | 128 |
| 28 | 256 | 1 | 256 |
| 28+ | 512 | 0 | 256 |
| 29 | 512 | 0 | 256 |
| 29+ | 512 | 1 | 256 |
| 30 | 512 | 1 | 512 |
| 30+ | 1024 | 0 | 512 |
| 31 | 1024 | 0 | 512 |
| 31+ | 1024 | 1 | 512 |
| 32 | 1024 | 1 | 1024 |
| 32+ | 2048 | 0 | 1024 |
| 33 | 2048 | 0 | 1024 |
| 33+ | 2048 | 1 | 1024 |
| 34 | 2048 | 1 | 2048 |
| 34+ | 4096 | 0 | 2048 |
| 35 | 4096 | 0 | 2048 |
| 35+ | 4096 | 1 | 2048 |
| 36 | 4096 | 1 | 4096 |
| 36+ | 8192 | 0 | 4096 |
| 37 | 8192 | 0 | 4096 |
| 37+ | 8192 | 1 | 4096 |
| 38 | 8192 | 1 | 8192 |
| 38+ | 16384 | 0 | 8192 |
| 39 | 16384 | 0 | 8192 |
| 39+ | 16384 | 1 | 8192 |
| 40 | 16384 | 1 | 16384 |
| 40+ | -32768 | 0 | 16384 |
| 41 | -32768 | 0 | 16384 |
| 41+ | -32768 | 1 | 16384 |
| 42 | -32768 | 1 | -32768 |
| 42+ | -2 | 0 | -32768 |
| 43 | -2 | 0 | -32768 |
| 43+ | -2 | 1 | -32768 |
| 44 | -2 | 1 | -2 |
| 44+ | -3 | 0 | -2 |
| 45 | -3 | 0 | -2 |
| 45+ | -3 | 1 | -2 |
| 46 | -3 | 1 | -3 |
| 46+ | -5 | 0 | -3 |
| 47 | -5 | 0 | -3 |
| 47+ | -5 | 1 | -3 |
| 48 | -5 | 1 | -5 |
| 48+ | -9 | 0 | -5 |
| 49 | -9 | 0 | -5 |
| 49+ | -9 | 1 | -5 |
| 50 | -9 | 1 | -9 |
| 50+ | -17 | 0 | -9 |
| 51 | -17 | 0 | -9 |
| 51+ | -17 | 1 | -9 |
| 52 | -17 | 1 | -17 |
| 52+ | -33 | 0 | -17 |
| 53 | -33 | 0 | -17 |
| 53+ | -33 | 1 | -17 |
| 54 | -33 | 1 | -33 |
| 54+ | -65 | 0 | -33 |
| 55 | -65 | 0 | -33 |
| 55+ | -65 | 1 | -33 |
| 56 | -65 | 1 | -65 |
| 56+ | -129 | 0 | -65 |
| 57 | -129 | 0 | -65 |
| 57+ | -129 | 1 | -65 |
| 58 | -129 | 1 | -129 |
| 58+ | -257 | 0 | -129 |
| 59 | -257 | 0 | -129 |
| 59+ | -257 | 1 | -129 |
| 60 | -257 | 1 | -257 |
| 60+ | -513 | 0 | -257 |
| 61 | -513 | 0 | -257 |
| 61+ | -513 | 1 | -257 |
| 62 | -513 | 1 | -513 |
| 62+ | -1025 | 0 | -513 |
| 63 | -1025 | 0 | -513 |
| 63+ | -1025 | 1 | -513 |
| 64 | -1025 | 1 | -1025 |
| 64+ | -2049 | 0 | -1025 |
| 65 | -2049 | 0 | -1025 |
| 65+ | -2049 | 1 | -1025 |
| 66 | -2049 | 1 | -2049 |
| 66+ | -4097 | 0 | -2049 |
| 67 | -4097 | 0 | -2049 |
| 67+ | -4097 | 1 | -2049 |
| 68 | -4097 | 1 | -4097 |
| 68+ | -8193 | 0 | -4097 |
| 69 | -8193 | 0 | -4097 |
| 69+ | -8193 | 1 | -4097 |
| 70 | -8193 | 1 | -8193 |
| 70+ | -16385 | 0 | -8193 |
| 71 | -16385 | 0 | -8193 |
| 71+ | -16385 | 1 | -8193 |
| 72 | -16385 | 1 | -16385 |
| 72+ | 32767 | 0 | -16385 |
| 73 | 32767 | 0 | -16385 |
| 73+ | 32767 | 1 | -16385 |
| 74 | 32767 | 1 | 32767 |

33
projects/03/a/Register.hdl Normal file
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@@ -0,0 +1,33 @@
// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/03/a/Register.hdl
/**
* 16-bit register:
* If load[t] == 1 then out[t+1] = in[t]
* else out does not change
*/
CHIP Register {
IN in[16], load;
OUT out[16];
PARTS:
Bit(in=in[0], load=load, out=out[0]);
Bit(in=in[1], load=load, out=out[1]);
Bit(in=in[2], load=load, out=out[2]);
Bit(in=in[3], load=load, out=out[3]);
Bit(in=in[4], load=load, out=out[4]);
Bit(in=in[5], load=load, out=out[5]);
Bit(in=in[6], load=load, out=out[6]);
Bit(in=in[7], load=load, out=out[7]);
Bit(in=in[8], load=load, out=out[8]);
Bit(in=in[9], load=load, out=out[9]);
Bit(in=in[10], load=load, out=out[10]);
Bit(in=in[11], load=load, out=out[11]);
Bit(in=in[12], load=load, out=out[12]);
Bit(in=in[13], load=load, out=out[13]);
Bit(in=in[14], load=load, out=out[14]);
Bit(in=in[15], load=load, out=out[15]);
}

569
projects/03/a/Register.tst Normal file
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@@ -0,0 +1,569 @@
// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/03/a/Register.tst
load Register.hdl,
output-file Register.out,
compare-to Register.cmp,
output-list time%S1.4.1 in%D1.6.1 load%B2.1.2 out%D1.6.1;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 1,
tick,
output;
tock,
output;
set in -32123,
set load 0,
tick,
output;
tock,
output;
set in 11111,
set load 0,
tick,
output;
tock,
output;
set in -32123,
set load 1,
tick,
output;
tock,
output;
set in -32123,
set load 1,
tick,
output;
tock,
output;
set in -32123,
set load 0,
tick,
output;
tock,
output;
set in 12345,
set load 1,
tick,
output;
tock,
output;
set in 0,
set load 0,
tick,
output;
tock,
output;
set in 0,
set load 1,
tick,
output;
tock,
output;
set in %B0000000000000001,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B0000000000000010,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B0000000000000100,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B0000000000001000,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B0000000000010000,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B0000000000100000,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B0000000001000000,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B0000000010000000,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B0000000100000000,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B0000001000000000,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B0000010000000000,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B0000100000000000,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B0001000000000000,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B0010000000000000,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B0100000000000000,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B1000000000000000,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B1111111111111110,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B1111111111111101,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B1111111111111011,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B1111111111110111,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B1111111111101111,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B1111111111011111,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B1111111110111111,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B1111111101111111,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B1111111011111111,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B1111110111111111,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B1111101111111111,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B1111011111111111,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B1110111111111111,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B1101111111111111,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B1011111111111111,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;
set in %B0111111111111111,
set load 0,
tick,
output;
tock,
output;
set load 1,
tick,
output;
tock,
output;